1. Field of the Invention
The invention relates to a method and apparatus for determining the write delay time of a memory, and more particularly to a method and apparatus for adjusting the write delay time in a DRAM (Dynamic Random Access Memory).
2. Description of the Related Art
A typical electrical product, such as a computer, has DRAMs (Dynamic Random Access Memory) for temporarily storing data, programs, and the like for the processor. The computer may operate more smoothly as the capacity of the DRAM gets larger. Therefore, the current computer is configured such that several DRAMs may be inserted into the computer for the user to conveniently expand according to the requirement. The DRAM may be, for example, a DDR (Double Data Rate) dynamic random access memory.
After a write command is issued to the memory, the memory will not be actually written until a period of delay time has elapsed so that the correctness of the data may be ensured. The required delay times of different memories are different because the manufactures thereof are different. Consequently, when the computer is started, the write delay time of the memory has to be identified so that the correctness of data reading/writing may be ensured.
FIG. 1 is a schematic illustration showing a write delay time of a memory. After the write command W is issued, the memory has a minimum write delay time tDQSSm. That is, after at least the write delay time tDQSSm has elapsed, a data strobe signal DQS may switched to a high level so that data may be written to the memory. The memory additionally has a maximum write delay time tDQSSM. That is, before the time elapses, the data strobe signal DQS has to be switched to a high level in order to write the data to the memory. Thus, the data written to the memory may be ensured to be correct as long as the write delay time falls between the minimum write delay time tDQSSm and the maximum write delay time tDQSSM.
Memory chips may be disposed on two opposite surfaces of one memory. One surface of the memory may be called as a rank of memory, which is enabled by a chip select signal (CS). For example, if the computer has four memories, and two opposite surfaces of each memory has memory chips, the computer may be regarded as having eight ranks of memories. When the computer is started, the write delay time ranges of the eight ranks of memories have to be checked, respectively, and finally the write delay time, which may be commonly used in the ranks of memories, may be determined.
FIG. 2 is a flow chart showing a conventional method for checking the write delay time of the memory. First, a write command is issued to the memory, as shown in step 210. Next, the apparatus waits for a write delay time, as shown in step 220. Then, a set of pattern, such as [01h 02h 03h 04h], is written to the memory according to the write command, as shown in step 230. Next, the pattern is read from the memory, as shown in step 240. Then, it is checked that whether or not the pattern is correct, as shown in step 250. If the read pattern is correct, the write delay time is passed, as shown in step 260; or otherwise the write delay time is failed, as shown in step 270. In step 280, the write delay time is changed, and the process goes back to step 210 for rechecking whether or not the changed write delay time is passed. Typically, it is possible to test the write delay time from a small one to a large one in order to find the minimum write delay time tDQSSm and the maximum write delay time tDQSSM for the memory.
Each rank of memory in the computer may find its minimum write delay time tDQSSm and maximum write delay time tDQSSM according to the method shown in FIG. 2. The commonly minimum write delay time is the maximum among the minimum write delay times, and the commonly maximum write delay time is the minimum among the maximum write delay times. Then, a common write delay time tDQSS is found in the commonly minimum write delay time and the commonly maximum write delay time. Thereafter, data may be written to the memory according to the common write delay time tDQSS when the computer is operating, and the written data may be ensured to be correct accordingly.
However, the checking method, which is mentioned above and typically executed by the BIOS (Basic Input/Output System) of the computer, consumes much time. The BIOS is located on a ROM (Read Only Memory) that is electrically connected to the south bridge. Because the speed for the CPU to read the command from the ROM is not quick enough and the BIOS further has to perform the identification by reading the pattern from the memory, the overall checking procedure for the write delay time is very slow, and the time for booting the computer will be lengthened.